Electrically insulating layers are required for many applications in semiconductor technology, in particular when forming integrated circuits in semiconductor substrates (for example in silicon substrates). If insulation layers are formed in an integrated circuit in which electrically conductive regions, in particular electrically conductive interconnects, are also included, coupling capacitances may result between adjacent interconnects and a dielectric layer arranged between them. The capacitance C of two parallel interconnects, the mutually adjacent surfaces of which are denoted by A and which are arranged at a distance d from one another, is, at a relative dielectric constant ε:C=εA/d  (1)
With ongoing miniaturization in silicon microelectronics, i.e. as the distance d between adjacent interconnects decreases, a high coupling capacitance C results in particular if the mutually adjacent surfaces A of the interconnects are large, i.e. if the interconnects run parallel to one another over a considerable length in the integrated circuit. By contrast, the coupling capacitance of two lines which cross one another is lower.
Problems with coupling capacitances are intensified by the ongoing miniaturization of integrated circuits. As the coupling capacitance increases, the propagation time of a signal in the electrical coupling means becomes ever longer, since this propagation time is determined by the product of resistance R and capacitance C (known as the “RC delay”).
As can be seen from equation (1), with fixed structure dimensions A, d, it is possible to reduce a coupling capacitance if the relative dielectric constant ε of the insulating material is reduced. It is therefore attempted to use materials with a low relative dielectric constant ε (known as “low-k materials”) as materials for insulation layers in integrated circuits.
Amorphous silicon dioxide (SiO2) with a relative dielectric constant of approximately 4.0 is often used as dielectric for electrically insulating metallic interconnects from one another. It is possible to further reduce the dielectric constant of a material for an electrically insulating layer if silicon oxide material which additionally contains fluorine, hydrogen or alkyl groups (in particular CH groups) is used for this purpose. This makes it possible to reduce the relative dielectric constant to as little as 2.5. Furthermore, organic materials, in particular polymers, such as for example SiLK™ (a dielectric produced by The Dow Chemical Company and marketed under the abovementioned trade name) or PBO (polybenzoxazole), are used, making it possible to achieve relative dielectric constants of 2.7. It is also possible for the “low-k materials” used to be materials based on silicon, such as for example a silicon-oxygen-fluorine compound, a silicon-carbon-oxygen-hydrogen compound, hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ).
The relative dielectric constant of electrically insulating layers can be reduced further by introducing cavities into the “low-k material”. The k value of the porous material is reduced further as a function of the proportion of the volume formed by the cavities or pores.
FIG. 1A illustrates a diagram 100 which is known from Steinhögl, W, Schindler, G (2001) “Towards Minimum k Values of Porous Dielectrics: A Simulation Study”, Advanced Metallization Conference, Oct. 9-11, 2001, Montreal. The k value khom of a homogenous material is plotted on the abscissa 101, and the associated k value kpor which is obtained if pores are introduced into the homogenous material is plotted on the ordinate 102. A first curve 103 shows the dependent relationship described if the cavities form 40% of the volume of the dielectric. A second curve 104 shows the dependent relationship described if the cavities form 50% of the volume of the dielectric, and a third curve 105 shows the dependent relationship if the cavities form 60% by volume of the dielectric. The curves 103 to 105 were obtained from model calculations calculated using effective medium approximation, an approximation method described in Aspnes, DE “Determination of Optical Properties by Ellipsometry” in “Handbook of Optical Constants of Solids”, Academic Press, 1985, pp. 104ff. The diagram 100 also shows a number of data points 106 which were obtained by calculation with the cavities forming 50% by volume, by numerically solving the Maxwell equations using a finite element simulation. It can be seen from FIG. 1A that the higher the proportion of the volume formed by cavities, the greater the extent to which the k value kpor in a porous material is reduced compared to the k value khom in a homogenous material. A k value of 2.0 can be reached by introducing pores into the dielectric.
However, this method is unable to satisfy the demands imposed by the ITRS Roadmap (“International Technology Roadmap for Semiconductors”) on the k value of an intermetal dielectric (IMD). ITRS is an institution which defines objectives for ensuring progress in integrated circuit technology. According to the ITRS Roadmap, in 2008 the demand will be for a k value of an intermetal dielectric of 1.5.
As illustrated in FIG. 1A, for an effective k value kpor, the host material, i.e. the homogenous, pore-free material, must have a k value khom of approximately 2.1, working on the basis of the pores forming 50% by volume. A material of this type is not currently known for use in silicon process technology.
In particular, the concept of gradually increasing the proportion of a porous dielectric which is formed by cavities is limited by the fact that if this proportion by volume becomes too high, the mechanical stability of the dielectric layer deteriorates and the heat conduction properties, which are of relevance to the dissipation of losses caused by resistance in interconnects, also deteriorate. Therefore, to achieve a sufficiently low k value, the solution of increasing the proportion of cavities to an ever greater extent is reaching its limits.
The dependent relationship between the effective k value keff and the pore cross-sectional area is shown in a semi-logarithmic illustration for different pore shapes and pore geometries in the diagram 110 shown in FIG. 1B.
The pore cross-sectional area is plotted in logarithmic form on an abscissa 111, and the effective k value keff is plotted on the ordinate 112. A first curve 113, a second curve 114, a third curve 115 and a fourth curve 116, which run through the corresponding data points, are plotted in the diagram 110. In all cases, the pores are assumed to form 50% by volume, and the host material is assumed to be silicon dioxide with a (homogenous) k value of 4.0.
The second curve 114 corresponds to the case of pores with a circular cross section, the third curve 115 corresponds to pores with a square cross-sectional area. The first curve 113 and the fourth curve 116 show the dependent relationship for a pore with a rectangular cross-sectional area, which in the case of the first curve 113 is oriented parallel to an external electrical field and in the case of the fourth curve 116 is oriented perpendicular to an external electrical field.
The simulation calculations which are described and known from Steinhögl, W, Schindler, G (2001) “Towards Minimum k Values of Porous Dielectrics: A Simulation Study”, Advanced Metallization Conference, Oct. 9-11, 2001, Montreal demonstrate that the effective k value decreases to a greater extent with the pores oriented perpendicular to an electric field than in the case of a parallel orientation between the direction in which the pores run and the electric field vector.
In other words, if elongate and oriented pores are used, it is possible to significantly reduce the effective k value keff without increasing the proportion of the volume which is made up of the pores. With the same proportion of pores by volume, a reduction of 13% is achieved with a pore aspect ratio of 4:1, and a reduction of 20% is achieved with a pore aspect ratio of 24:1. If the pores are randomly oriented, there is no advantage over round pores (aspect ratio 1:1). In this case, the same mean k value is obtained.
However, the formation of oriented pores in a dielectric with cross-sectional areas sufficiently small for preferably a multiplicity of such pores to be arranged between adjacent interconnects of an integrated circuit, which are typically arranged at a distance F from one another, imposes considerable technological demands. In this context, F denotes the minimum feature sizes that can usually be achieved using a specific technology.
The following process for producing a porous dielectric is known from the prior art. Two liquid components, of which one is dielectric in the solidified state and the other is, for example, a pore-forming agent, are mixed and brought to an elevated temperature at which only the first component solidifies, and in so doing encloses liquid pore-forming agent. If the inclusions of pore-forming agent are converted into the gas phase, what remains is a porous dielectric.
However, the process described cannot be used to produce oriented pores, which have particularly advantageous properties (cf. FIG. 1B), and the process is limited to dielectrics which are in a settable liquid phase.
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